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Adaptation of digital predistorter to linearize amplifiers using comparator
Jagla, Lukáš ; Ayöz, Suat (oponent) ; Götthans, Tomáš (vedoucí práce)
This master’s thesis presents a development of a new hardware implementing a comparator in the feedback path of DPD systems. A new architecture is proposed and selected features are verified by simulations. Subsequently, the suitable components are selected for high-speed performance and an acquisition module is proposed. A 4-layer PCB is well designed, manufactured, and prepared for further work. Afterwards, an appropriate firmware is developed for signal transmission and data acquisition. The obtained results serves for the evaluation of the proposed architecture and for its future implementation in real DPD systems.
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Digital Predistorters with Low-Complexity Adaptation
Král, Jan ; Springer, Andreas (oponent) ; Roblin, Patrick (oponent) ; Götthans, Tomáš (vedoucí práce)
Modern communication systems often require digital predistorters (DPDs), advanced signal-processing units, to satisfy stringent demands on transmitter linearity and efficiency. Nevertheless, DPD significantly increases the hardware and computational complexity of transmitters, which leads to increased power consumption and expenses. Therefore, we propose methods to achieve lower hardware and computational complexity of DPD adaptation. The principle of real-valued feedback samples allows for saving one of two originally-needed feedback analogue-to-digital converters (ADCs), which implies reduced transmitter complexity and power consumption. Furthermore, the hardware and computational complexity can be reduced if the feedback samples for the DPD adaptation are undersampled and carefully selected. The proposed techniques select samples based on histograms and can reduce the required number of feedback samples to a few tens. The provided analyses show approximately 400-times reduced computational complexity achieved by the sample selection and 40-times reduced power consumption of the undersampling feedback ADCs. The real-valued feedback, its undersampling, and sample selection constitute fundamental principles of the proposed DPD adaptation with a level-crossing ADC, which is realised by a simple comparator. Replacing the conventional ADCs with a comparator significantly reduces the design complexity and power consumption. All the proposed and described techniques are accompanied by simulations, usually confirmed by measurements on real hardware, and compared with state-of-the-art methods. The final discussion analyses the limitations, usability and advantages of the proposed techniques. It shows that reducing complexity might not be universally applicable and all the design constraints and specifications must be carefully assessed.
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Digital Predistorters with Low-Complexity Adaptation
Král, Jan ; Springer, Andreas (oponent) ; Roblin, Patrick (oponent) ; Götthans, Tomáš (vedoucí práce)
Modern communication systems often require digital predistorters (DPDs), advanced signal-processing units, to satisfy stringent demands on transmitter linearity and efficiency. Nevertheless, DPD significantly increases the hardware and computational complexity of transmitters, which leads to increased power consumption and expenses. Therefore, we propose methods to achieve lower hardware and computational complexity of DPD adaptation. The principle of real-valued feedback samples allows for saving one of two originally-needed feedback analogue-to-digital converters (ADCs), which implies reduced transmitter complexity and power consumption. Furthermore, the hardware and computational complexity can be reduced if the feedback samples for the DPD adaptation are undersampled and carefully selected. The proposed techniques select samples based on histograms and can reduce the required number of feedback samples to a few tens. The provided analyses show approximately 400-times reduced computational complexity achieved by the sample selection and 40-times reduced power consumption of the undersampling feedback ADCs. The real-valued feedback, its undersampling, and sample selection constitute fundamental principles of the proposed DPD adaptation with a level-crossing ADC, which is realised by a simple comparator. Replacing the conventional ADCs with a comparator significantly reduces the design complexity and power consumption. All the proposed and described techniques are accompanied by simulations, usually confirmed by measurements on real hardware, and compared with state-of-the-art methods. The final discussion analyses the limitations, usability and advantages of the proposed techniques. It shows that reducing complexity might not be universally applicable and all the design constraints and specifications must be carefully assessed.
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Acquisition System For Adaptation Of Digital Predistorter To Linearize Amplifiers Using Comparator
Jagla, Lukáš
This paper presents a design of an acquisition system for adaptation of a digital perdistorter implementing a comparator in the feedback path. The key parts of an acquisition chain are verified by simulations and suitable components are chosen for high-speed performance. Subsequently, a printed circuit board is designed, manufactured and prepared for further testing. Finally, an appropriate firmware is developed to evaluate the proposed hardware and to acquire data for digital predistorter adaptation.
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Evaluation Of Influence Of Anti-Aliasing And Reconstruction Filters On Digital Predistortion
Král, Jan
Present wideband and spectrally-efficient communication systems require linear transmitters. As power amplifiers are naturally nonlinear, the linear transmitter is often achieved by application of a digital predistorter (DPD). DPDs require system bandwidth to be higher than communication bandwidth. We provide an evaluation of influence of the reconstruction and anti-aliasing filter on quality of predistortion process. Our results show that the generally accepted rule is too demanding and the actual required filters bandwidth is lower. This has direct impact on required sampling rates of system converters.
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Adaptation of digital predistorter to linearize amplifiers using comparator
Jagla, Lukáš ; Ayöz, Suat (oponent) ; Götthans, Tomáš (vedoucí práce)
This master’s thesis presents a development of a new hardware implementing a comparator in the feedback path of DPD systems. A new architecture is proposed and selected features are verified by simulations. Subsequently, the suitable components are selected for high-speed performance and an acquisition module is proposed. A 4-layer PCB is well designed, manufactured, and prepared for further work. Afterwards, an appropriate firmware is developed for signal transmission and data acquisition. The obtained results serves for the evaluation of the proposed architecture and for its future implementation in real DPD systems.
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Direct Learning Architecture For Digital
Predistortion With Real-Valued Feedback
Král, Tomáš Král, Jan
The power efficiency is a key parameter of modern comunication systems. Efficient nonlinear power amplifiers are linearised using digital predistorters. Conventional predistorters require two ADCs in the feedback. In this paper we have proposed a modification of the direct learning architecture using solely one ADC in the feedback and an RF mixer instead of a quadrature mixer. This allows us to minimise the system complexity and power consumtion and maximise the efficiency. The proposed architecture has been verified experimentally and compared to the conventional digital predistorters. We have shown that it can achieve same linearisation performance as the conventional architecture with two ADCs. Moreover the proposed method outperformed the conventional DPD with indirect learning architecture.
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Digital Predistortion Experiments with MATLAB-controlled Software Defined Radio
Pospíšil, Martin
This paper presents the experiments with digital predistortion for power amplifier linearization. It describes the architecture of used measurement setup based on the software defined radio USRP N200 with the focus on our custom MATLAB-based control of the USRP through UDP packets. Measurement results obtained for the 800 MHz power amplifier linearized by memory polynomial predistorter are presented, but the prepared framework to control of USRP in MATLAB can of course be used for experiments not only with such type of predistorter but for wide range of experiments where the USRP serves as the receiving/transmitting unit.
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